High precision floating-point computing increases numerical stability and is very useful in scientific computing. The VRP (VaRiable Precision) is a RISC-V accelerator designed to speed up this type of operation (up to 512 bits of mantissa and 18 bits of exponent). This work aims to fix the major bottleneck of this accelerator: the floating point multiplier, which is much slower than the rest of the other hardware operators. The product of the two mantissas currently iterates over a single 64-bit multiplier, and it requires a latency up to 64 clock cycles to compute the result, while the other units requires at most 4 clock cycles.