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Acceleration of an OFDM modulator on a Xilinx FPGA

Giovanni Luca Amato

Acceleration of an OFDM modulator on a Xilinx FPGA.

Rel. Luciano Lavagno, Mihai Teodor Lazarescu. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

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Today’s technology rush and the rise of the IoT leads us to find new solutions to achieves significant speedup and resource savings over the traditional implementation. In fact, this can result computationally intensive when we talk about digital signal processing, simulation and modeling or machine learning. Hardware acceleration is dedicated hardware designed to perform specific functions more efficiently when compared to software running on a general-purpose CPU. Central Processing Unit are projected to be used in different tasks, but to archive that the trade-off is a loss of performance in terms of in terms of latency, throughput, and resource utilization respect to dedicate hardware limited to a single task. Using High Level Synthesis (HLS) to generate hardware designs enables the use of a high-level programming language instead of traditional hardware description languages. HLS tool analyses the design specification and automatically generates hardware implementation based on the performance requirements. The objective of our research group is 3GPP 5G Channel Model Acceleration. This task was mainly focused on the acceleration of the channel model using HLS tools for Xilinx and Intel FPGA platforms. Given the complexity of this project each member of the team focusing on a particular component of the channel. My role was to implement orthogonal frequency-division multiplexing (OFDM) modulator and demodulator designs to be inserted as accelerated channel model modules. The module is characterized by Direct or Inverse Fast Fourier Transform (FFT/IFFT) calculation on a large asset of data, implemented using a dedicated IP. Using Vitis HLS, starts from a Matlab algorithm, was implemented a C++ implementation of the OFDM algorithm, optimized for the HLS (High Level Synthesis). The generated Register Transfer Level (RTL) design was tested with simulation and on board before to be nested in the channel chain. All modules developed are described in a dedicated chapter and each one with all the test performed, followed by a comparison between different implementation.

Relators: Luciano Lavagno, Mihai Teodor Lazarescu
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 84
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/26897
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