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Power and Area Optimization of a Neural Network-Based Digital Pre-Distorter for RF Power Amplifiers

Alessio Cicero

Power and Area Optimization of a Neural Network-Based Digital Pre-Distorter for RF Power Amplifiers.

Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2023

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Transmitter linearity is of major importance in wireless communications, and the main contributor to the non-linearity is the power amplifier (PA). Non-linearity reduces the system's overall efficiency and can lead to degradation of bit-error rate and data throughput. Digital pre-distortion (DPD) is a technique which allows compensating for the PA non-linearity with an overall power efficiency increase. Correcting the PA behaviour is a challenging task, and neural networks (NNs) have been proven to be highly effective in doing so. But due to the high amount of multiply and accumulate units, the area and power required by the hardware implementation of a NN predistorter is usually not negligible compared to the PA efficiency gains. Using DPD is useful only if the savings in terms of power due to the efficiency increase are bigger than the DPD power consumption. The objective of this work is to explore various quantization approaches to optimize the power and area of a NN-based DPD. The starting NN is the augmented real-valued time-delay neural network (ARVTDNN), which is a simple but effective architecture. In this work, three different approaches are evaluated, comparing their area and power consumption with a baseline, obtained with the post training quantization (PTQ). They are first introduced at the algorithmic level in order to minimize the bit-resolution and in a second step, a DPD engine has been implemented in hardware in order to assess the savings in area and power using synthesis and simulations. The first approach explored is quantization aware training (QAT), based on retraining after the quantization. The second approach, power of two quantization, is used to reduce the amount of hardware needed per every multiplication by quantizing all the weights to the closest power of two, allowing the replacement of the multipliers with barrel shifters. The third approach is based on changing the system level view of the problem. A linear bypass is introduced to the model and added to the nonlinear NN output, reducing the dynamic range of the output signal of the NN. The results reported in this work show the interdependent effectiveness of those methods. A final realization based on this prestudy is presented by combining the different approaches.

Relators: Guido Masera
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 90
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Nokia Bell N.V.
URI: http://webthesis.biblio.polito.it/id/eprint/26635
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