Iacopo Guglielminetti
Evaluating the cell-aware fault coverage of functional test programs.
Rel. Matteo Sonza Reorda, Michelangelo Grosso, Riccardo Cantoro. Politecnico di Torino, Master of science program in Computer Engineering, 2022
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Abstract
Testing an integrated circuit (IC) is the process aiming at identifying faulty products that do not behave according to specifications. During the fabrication of IC, physical defects could arise. Since physical defects are difficult to work with, logical faults have been created. The way a logical fault models a physical defect is called fault model. After creating a fault model, the testing flow continues with fault detection with a fault simulator. When the fault is present in a model, it creates a misbehaviour observable on the outputs. To perform fault detection we need to apply tests on the unit under test.
For years many models were proposed: bridge, stuck-at-faults, transition, N-detect, timing-aware, and layout-aware are just an example
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