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3D Junctionless-FET technology: A comparative TCAD simulation study with FinFET and NSGAAFET

Luca Scognamiglio

3D Junctionless-FET technology: A comparative TCAD simulation study with FinFET and NSGAAFET.

Rel. Gianluca Piccinini, Marco Vacca, Fabrizio Mo, Chiara Elfi Spano. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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The progress of semiconductor electronics devices has been marked by rapid improvement in terms of performance since the first MOSFET was invented in 1960. In the last decades the down-scaling of the transistor has led to increasing performance in electronic systems while following the Moore’s Law. However, this trend reached its limit, when the performance degradation of junction based metal-oxide-semiconductor field-effect-transistor (MOSFET) increased due to channel scaling. The limitations of the device related to the rising short channel effects (SCEs) are the threshold voltage (VTH) roll off, subthreshold current and drain-induced-barrier-lowering (DIBL). Moreover, process challenges concerning the fabrication of ultra steep p-n junctions restricts its functionality in the fabrication of the transistor itself. The increasing demand for high integration density, high performance and low power consumption can be achieved with Gate-All-Around (GAA) FETs such as FinFET and NanoSheet GAAFET (NSGAAFET), thanks to a better control of the channel transport via fully surrounding gate. Further challenges emerge during fabrication processes in the next technology nodes when decreasing the size of transistors. The junctions (p-type and n-type) will get closer, which means that the requirement of extremely high gradients in doping concentration to create the heavily doped source/drain regions becomes unfeasible. One of the solution to address the physical limitations of junction based MOSFET, while achieving better performance, has been proposed by designing a FET without junctions known as junctionless field-effect-transistor (JLFET). Combining the JLFET with the electrostatic gate control of multigate structures like GAA, it is possible to obtain a device with improved SCEs immunity and tunable VTH, obtained by varying the channel width. In this work, the electrical performance of junctionless FinFET (JL-FinFET) and NSGAAFET (JL-NSGAAFET) are compared with the conventional FinFET and NSGAAFET. A fabrication process simulation of the devices with highlights of different steps that could replace the current manufacturing of conventional transistors is provided. The analysis carried out using Synopsys Sentaurus (8; 9) are developed to report electrical characteristics of each devices under exam. Thereafter, the results have been compared to have an idea of how certain parameters affect the performance of each transistor. Finally, there are presented some thoughts about the possible evolution of technologies and future works that may help investigating the application of junctionless devices.

Relators: Gianluca Piccinini, Marco Vacca, Fabrizio Mo, Chiara Elfi Spano
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 118
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/25434
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