Current state-of-the-art integrated circuit complexity induced semiconductor companies to make large investments in Electronic Design Automation. In particular, automation software helps to easily handle design flows and enhances scalability. On the other hand, the optimization strategies embedded in such tools are not effortlessly customizable. In order to achieve the best results in terms of Power, Performance, Area, it is necessary to implement dedicated procedures. This work proposes a specific framework devoted to improving PPA metrics during the timing closure step of the physical design stage. The methodology aims at reducing the drive strength of standard cells while ensuring time constraints are not violated, not to hinder the designed functionality.