Modern microprocessors exploit Out-of-Order (OoO) execution to address the "memory wall" and enhance performance by increasing the number of instructions executed at the same time. The implementation of this technique requires the introduction of specific structures, the Load and Store Queues (LSQs), to buffer load and store instructions and ensure the memory is updated in program order, despite OoO execution. Increasing the number of in-flight instructions implies scaling up LSQs and the logic necessary to detect and resolve memory order violations, making these structures a bottleneck in terms of both power and latency. The goal of this thesis is the investigation of new techniques to reduce LSQs power consumption in next-generation Arm microprocessors.