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Tunneling Field-Effect Transistor: digital circuit analysis and ambipolarity impact

Roberta Antonina Claudino

Tunneling Field-Effect Transistor: digital circuit analysis and ambipolarity impact.

Rel. Gianluca Piccinini, Chiara Elfi Spano, Fabrizio Mo. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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In the past decades, searches to overcome the limits of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has been carried out. Tunnelling Field Effect Transistors (TFETs) have been considered as a possible candidate to replace MOSFET. Based on band-to-band tunnelling, TFET can achieve lower Subthreshold Slope, below the 60mV/dec limit of the MOSFETs, higher Ion/Ioff ratio and so has been considered for low power application. A drawback of TFET is the ambipolarity: the device turns on for both positive and negative voltages applied to the gate. In this work, a digital circuit performance evaluation of TFETs has been performed in Cadence Virtuoso. The well-established Notre Dame Model by Hao Lu et al. has been used to carry out the simulations. This Model is implemented in Verilog-A and the characterized device AlGaSb/InAs, present in the library, has been exploited. To understand the impact of ambipolarity in circuit based on TFETs, all the main logic gates were addressed. From the obtained results, ambipolarity strongly impacts on correct functioning of logic operations. Thus, ameliorated devices were considered. In particular, devices with symmetric ambipolar transcharacteristics show a correct logic behavior but still have the drawback of a significant greater dissipated power during switching operations in comparison with CMOS logic gates. Only when technological ameliorations are capable of strongly reduce ambipolarity the basic gates permit to achieve all the main advantages of TFET tecnology, e.g., extremely low dissipated power. Future works should be oriented to overcome the intrinsic low Ion of TFET technology to achieve high performance and low power digital circuits.

Relators: Gianluca Piccinini, Chiara Elfi Spano, Fabrizio Mo
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 89
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/23549
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