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Design and Development of a DSP Accelerators Array in a FPGA-based Clustered Architecture for Space Applications

Antonino Catanese

Design and Development of a DSP Accelerators Array in a FPGA-based Clustered Architecture for Space Applications.

Rel. Maurizio Zamboni. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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This thesis focuses on the design of an array of accelerators for Compute-Intensive Telecom Applications within the framework of a project founded by ESA and carried out in Argotec, an Italian Aerospace Company developer and manufacturer of new solutions for astronaut comfort and the manufacturing of micro and nano satellites for deep space. In detail, this project aims at providing a novel architectural approach based on a cluster of Field Programmable Gate Arrays (FPGA), which are programmable devices that provide high flexibility and high performance thanks to their integration and re-configurability. This architectural model could enable the usage of non-space-grade Commercial-of-the-Shelf (COTS) devices in long-life missions in harsh radiation environments by leveraging the resource redundancy and distribution enabled by clustering methods, together with the possibility of different mitigation technique application. Commercial-graded devices are made up of the newest and most performing technology on the market and their use in space environment gives advantages both in terms of performances and costs. In detail, the present thesis focused on the design of a system with high computing capability by leveraging hardwired primitives present in state-of-the-art FPGAs for Digital Signal Processing (DSP). These DSP units are attractive candidates to balance the programmability typical of dedicated arithmetic logic units and the high performance of dedicated hardware thanks to the possibility of implement a variety of processing modes. Overall, each DSP unit together with a specific management which will provides signals and controls for data computations create a Programmable Functional Unit (PFU) which is the the key element on which this thesis is based. The main aim of this thesis is the development of a programmable and scalable accelerator structure capable of executing a range of tasks for telecom applications in space environment. Furthermore, the studies were also carried out with the aim of optimising the architecture presented with a view to maximising performance and minimising the resources used. In order to achieve these goals, different design solutions were investigated, all of which converged on a replicable architecture inside the target device via a versioning strategy that allowed for the most efficient use of resources and, as a result, the array's appropriate implementation. Furthermore, this design flow resulted in the best trade-off in terms of flexibility, granularity and resource utilisation. Finally, during the versioning process and on the final design, it was verified that the project's performance requirements were satisfied.

Relators: Maurizio Zamboni
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 107
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Argotec srl
URI: http://webthesis.biblio.polito.it/id/eprint/23548
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