This thesis focuses on the design of an array of accelerators for Compute-Intensive Telecom Applications within the framework of a project founded by ESA and carried out in Argotec, an Italian Aerospace Company developer and manufacturer of new solutions for astronaut comfort and the manufacturing of micro and nano satellites for deep space. In detail, this project aims at providing a novel architectural approach based on a cluster of Field Programmable Gate Arrays (FPGA), which are programmable devices that provide high flexibility and high performance thanks to their integration and re-configurability. This architectural model could enable the usage of non-space-grade Commercial-of-the-Shelf (COTS) devices in long-life missions in harsh radiation environments by leveraging the resource redundancy and distribution enabled by clustering methods, together with the possibility of different mitigation technique application.