Nowadays ASICs are present in any device around us, this trend will increase as IoT becomes more widespread. Chip complexity is increasing and time to market is shrinking, this leads to new challenges for silicon engineers, requiring designers to spend 6 to 8 months on design cycle. Reduction in design time can only occur if new design flows are identified, which allow identification of the power-performance-area (PPA) space at an early stage of the design. Misjudgment at a late stage of the project is not permissible and would lead to project failure. This thesis work identifies a design flow that allows estimating power consumption during the architectural derivation of digital IPs, enabling architectural corrections to be made before even writing a line of HDL code.