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Design of a high-speed data buffer based on DDR memories for real-time processing of hyperspectral data and its implementation in a radiation-tolerant FPGA

Laura Chisciotti

Design of a high-speed data buffer based on DDR memories for real-time processing of hyperspectral data and its implementation in a radiation-tolerant FPGA.

Rel. Guido Masera, Davide Fiorini. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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In the space environment, during the image acquisition, the hyperspectral payloads need to process a data flow, which could swing between hundreds of Mbit/sec and some Gbit/sec. In this scenario, one of the key aspects is to find the correct dimension of the memory buffers, based on access speed and dimension, in order to optimize the payload and guarantee the time allocation of the whole sequence of tasks, which have to be executed between the rough data sending by the detector and the moment in which the processed data are sent to the platform. The hyperspectral payload called CHIME (Copernicus Hyperspectral Imaging Mission for the Environment), implemented by the Leonardo S.p.A. for the European Space Agency (ESA), needs to access a high-speed buffer concurrently in order to memorize the data coming from the detector, execute a spectral editing/binning, fix bad pixels, apply some coefficients to obtain a linear calibration of their radiometric value and read again the data, grouping them in homogeneous packages before shipping them towards the mass memory of the satellite. All the tasks have to be executed in real-time with approximately 8 Gbit/sec input data flow. The intention of this work of thesis is to design the high-speed data buffer based on DDR3 memory banks, which has to be projected, thus, it could be subsequently implemented in a radiation-tolerant FPGA, in particular, in an FPGA RTG4150 of the Microchip. This high-speed data buffer is a controller implemented in VHDL, which has to make available to the other blocks two different interfaces, through which it is possible the writing and the reading: a Direct Access (DA) interface and a First In First Out (FIFO) one. Moreover, on the other side, the controller interfaces with a hardware macrocell FDDR of the FPGA Microchip RTG4150, which has the aim to manage, in an efficient way, the writing and the reading of the data burst in the DDR3 memory banks. Therefore, since the FDDR block could be accessed only through an AXI interface, another of the high-speed data buffer tasks is to translate the signals deriving from the Direct Access interface or the FIFO one into signals of the AXI interface. Another task of this controller is to manage the concurrent accesses to the DDR3 memory banks, in fact, inside the controller there is also an arbiter block, which, based on the Round Robin algorithm, coordinates the concurrent readings and concurrent writings, when two users want to access one through the Direct Access interface and one through the FIFO interface both to read or write to the same sources. All the project has to follow the ECSS-Q-ST-60-02C Standard, which is one of the European Cooperation for Space Standardization.

Relators: Guido Masera, Davide Fiorini
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 139
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: LEONARDO SPA
URI: http://webthesis.biblio.polito.it/id/eprint/23437
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