With the increasing complexity of modern VLSI designs, verification is becoming one of the biggest challenges for large semiconductor companies. Since they need to get the design in the market within a reasonable timescale, and the system is too complex to cover all possible input combinations and state transitions, different verification methodologies have to be mixed in order to exploit different advantages and to cover the holes left by other methods. One of these (that is now becoming mandatory to try a huge number of input patterns in an acceptable time-to-market) is the FPGA prototyping. With this technology it is possible to achieve a throughput of two orders of magnitude higher than in simulation, with the disadvantage of a limited internal visibility.