Study and Development of a Radiation-Hardened Implementation of the RISC-V Processor on Reconfigurable Devices

Eleonora Vacca

Study and Development of a Radiation-Hardened Implementation of the RISC-V Processor on Reconfigurable Devices.

Rel. Luca Sterpone, Corrado De Sio, Sarah Azimi. Politecnico di Torino, Master of science program in Electronic Engineering, 2021

Preview

PDF (Tesi_di_laurea) - Thesis
Licence: Creative Commons Attribution Non-commercial No Derivatives.
Download (3MB) | Preview

Abstract

Nowadays, aerospace companies are looking for the best hardware and software solutions that satisfy on one hand their hunger for performance and efficiency and on the other hand solutions require to be verifiable, economical, safe. In this context, RISC-V ISA has emerged as a good candidate capable of meeting these prerequisites, with the addition of being an open source alternative to commercial ISAs. Another prerogative that a design must possess to be used in the field of aerospace is reliability. A reliable system is widely viewed to be a system that tolerates faults; in the aerospace applications faults may occur as consequence of radiations which manifest themselves as Single Effect Upset (SEU).

Having at hand a SoC design of a RISC-V implementation for FPGA, the thesis work starts with initial investigation of the RISC-V architecture and how it has been placed into FPGA resources