This study consists in the implementation of a compact model for 14 nm Bulk FinFET tech- nology, from room temperature to low temperature, as well as the characterization of these devices, nFET and pFET. Additionally, to the investigation of di_erent cryogenic models, a correction due to the parasitic resistances has been included. Previous measurements have been exploited to _t the drain current and subthreshold slope models. The drain current model greatly captures the pFET and nFET behaviors, over the full range of temperature. A slight deviation observed at high gate bias on the output characteristic led us to inves- tigate self-heating e_ects.