Efficient LDPC implementation on FPGAs for 5G networks

Ze Chen

Efficient LDPC implementation on FPGAs for 5G networks.

Rel. Luciano Lavagno, Mihai Teodor Lazarescu. Politecnico di Torino, Master of science program in Electronic Engineering, 2021

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Abstract

Low-Density Parity-Check code, known as LDPC code, or Gallager code, has been introduced by Robert Gallager in 1963, after being forgotten for 19 years, Michael Tanner rediscovered Gallager’s paper and did research on LDPC code from the perspective of graph theory in 1981. Then in 1996, Mackay, Spielman and Wiberg found out the advantage of LDPC code in terms of its low linear decoding complexity, and its excellent performance which closes to Shannon Limit. Since then LDPC code was massively studied in research field, nowadays it became one coding standard of 5G technology. Previous work was focusing on hardware acceleration on FPGA, based on a software implementation of LDPC decoder provided by OpenairInterface Software Alliance Consortium(OAI), specifically two versions of code, Advanced Vector eXtension2(AVX2) solution and Compute Unified Device Architecture(CUDA) solution.

For AVX2 version, by exploiting High Level Synthesis(HLS) tool provided by Xilinx, Hardware Description Language(HDL) was generated automatically by the tool converting from C code, the work was aborted due to the unsynthesizability of source code, then the CUDA solution was adopted, imported in OpenCL language then optimized inside the SDAceel development environment by Xilinx, finally bitstream was generated and tested on FPGA board