Giorgio Perrone
Characterization and Performance Evaluation of Programmable Logic-in-Memory architectures.
Rel. Maurizio Zamboni, Marco Vacca, Giovanna Turvani. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021
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Abstract
Nowadays, one task to fulfill is to overcome the bottleneck of the Von Neumann architecture. The most critical aspect of this kind of structure is that the operating unit has greatly improved its performance in recent years, while memories couldn't follow this trend. For this reason, especially in data-intensive applications, the memory is not able to provide data as fast as the operating unit can compute them, leading to a worsening of performance. A possible solution to this bottleneck is the Logic-in-Memory (LiM) approach. It consists of merging processing elements and storage together to get a hybrid memory capable of both storing and computing data.
The state-of-the-art surrounding the Von Neumann Architecture and the LiM idea is analyzed, trying to find out a set of possible solutions adopted in the past to overcome this bottleneck
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