Politecnico di Torino (logo)

Characterization and Performance Evaluation of Programmable Logic-in-Memory architectures

Giorgio Perrone

Characterization and Performance Evaluation of Programmable Logic-in-Memory architectures.

Rel. Maurizio Zamboni, Marco Vacca, Giovanna Turvani. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021

PDF (Tesi_di_laurea) - Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (1MB) | Preview

Nowadays, one task to fulfill is to overcome the bottleneck of the Von Neumann architecture. The most critical aspect of this kind of structure is that the operating unit has greatly improved its performance in recent years, while memories couldn't follow this trend. For this reason, especially in data-intensive applications, the memory is not able to provide data as fast as the operating unit can compute them, leading to a worsening of performance. A possible solution to this bottleneck is the Logic-in-Memory (LiM) approach. It consists of merging processing elements and storage together to get a hybrid memory capable of both storing and computing data. The state-of-the-art surrounding the Von Neumann Architecture and the LiM idea is analyzed, trying to find out a set of possible solutions adopted in the past to overcome this bottleneck. The Programmable Logic-in-Memory (PLiM), an architecture developed at the polytechnic university of Turin, is taken into account since it demonstrated to be very efficient to lighten the Von Neumann limitations. In this approach, the processing unit and the memory are no longer seen as two different entities, since the memory becomes also capable of performing some operations directly inside its array. This is achieved thanks to some computational blocks which are able to handle and process data directly inside the memory space, reducing the memory accesses which are expensive in terms of timing and energy. PLiM is presented and tested with different kinds of algorithms to evaluate which of them fit better the architecture and which not. For each benchmark, performance values are evaluated in terms of power and energy dissipation. In the end, a comparison between the PLiM approach and a standard architecture, where memory and processor are kept separated, is carried out. In particular, considering the implementation of the same algorithm, PLiM leads to notable advantages compared to a RISC-V architecture, both in terms of the application execution time and energy consumption. For some applications, PLiM can stand up to comparison with some structures built with the specific intent of being accelerators for those applications, demonstrating to be a very efficient and flexible solution also in the application-specific environment.

Relators: Maurizio Zamboni, Marco Vacca, Giovanna Turvani
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 93
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/19231
Modify record (reserved for operators) Modify record (reserved for operators)