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GP-LiMA: A General Purpose Architectural Model leveraging the Logic-in-Memory Approach

Angela Guastamacchia

GP-LiMA: A General Purpose Architectural Model leveraging the Logic-in-Memory Approach.

Rel. Mariagrazia Graziano, Marco Vacca, Giovanna Turvani. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021

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Abstract:

In the last years, the technological drivers that have underpinned the unceasing enhancement of processing systems performance are no longer sufficient to support the usual exponential trend. One of the main issues is linked to the standard Von Neumann organisation that is based on a clear division between the processing unit and the memory. This layout implies a constant data stream between CPU and data memory that are affected by a significant performance gap. The massive number of memory accesses results in power and latency overheads, further exacerbated in data-intensive applications. This thesis work presents the design of a novel architectural model that puts the spotlight on an alternative computing approach, i.e. the Logic-in-Memory (LiM). This paradigm lies in the integration of processing elements inside the memory, delegating parts of the required elaboration directly to the memory itself, so allowing to reduce both execution time and energy consumption. With LiM the number of memory accesses is cut off, and the full memory bandwidth can be exploited to parallelise data-intensive tasks. However, the LiM approach integration inside the systems can be very complex. Since actual LiM architectures are customised for a specific algorithm, each time a new application is demanded, a complete re-design from scratch is required. During this thesis, a specific case study was investigated, showing a preliminary solution for this issue: the Programmable LiM (PLiM). It provides an already engineered skeleton, easily adaptable by the hardware designer to the specific tasks at hand. The PLiM structure is composed of the LiM Array, capable of running the application parallel tasks, and the control part that properly handles the processing. The LiM Array comprises a sequence of single word locations, called Smart Rows, made of both storing and computing elements. The Smart Row is the item that can be quickly modified by inserting a customised block to implement the required function. Then, since the same instruction simultaneously drives all the Smart Rows, the PLiM computing model is the SIMD (Single Instruction Multiple Data) one. In this thesis, the PLiM was tested through several benchmarks, demonstrating to be efficient in running highly parallel tasks while struggling to execute the more sequential ones. Thus, an improved architectural model is proposed, called GP-LiMA (General Purpose Logic-in-Memory Architecture), which is intended to map a wider set of algorithms. The programming generality is reached by providing an ad-hoc set of functions helpful for most applications. Differently from PLiM, the GP-LiMA array is arranged in a matrix of densely interconnected Smart Blocks, which act similarly to the PLiM Smart Rows. The single Smart Block is supplied with a default structure, resembling a small processor. The combination of the flexible programmable interconnections and the Smart Blocks guarantee the programming generality, further reducing processing times and energy consumptions. The speedup is also achieved thanks to the M-SIMD (Multiple - SIMD) computing model, for which the Smart Blocks are enabled to run different instructions simultaneously. Performance comparisons between GP-LiMA and PLiM are proposed. In the analysed sequential benchmarks, the results obtained by the GP-LiMA show improvements ranging from 64% to 80% in terms of energy/sample, demonstrating very high efficiency and empowered computing capabilities.

Relators: Mariagrazia Graziano, Marco Vacca, Giovanna Turvani
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 226
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/19228
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