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Interfacing a Neuromorphic Coprocessor with a RISC-V Architecture

Andrea Spitale

Interfacing a Neuromorphic Coprocessor with a RISC-V Architecture.

Rel. Gianvito Urgese, Evelina Forno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2021

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The concept of neural network is nowadays spread everywhere. Commonly meant as a mean to provide what is called artificial intelligence, neural network constitute one of few state of the art technologies which are constantly growing in complexity and efficiency to overcome new challenges, providing fascinating services and features, ranging from image classification and manipulation, up to speech recognition and many more that are still being explored. A neural network is a computing system which takes inspiration from the human brain, exploiting its parallel interconnections to solve complex data problems, modifying its internal parameters (training phase) in order to recognize unknown input data with higher accuracy (inference phase). Spiking Neural Networks (SNN) represent an emerging class of neural networks, coming from neuroscience research and aiming at accurately reproducing both static and dynamic behaviours of human brain neurons. Initially conceived to help neuroscientists enrich their knowledge on the human brain structure and working principles, SNNs have gathered attention in the computer science community, for several reasons: power efficiency, continuous learning, natural support for spatio-temporal input. Internet of Things (IoT) oriented applications, running on smart devices capable of analyzing data in real time with limited power resources, are predicted to be those that will benefit a lot from the adoption of SNN based solutions. Indeed, since spikes are sparse in time and space, the network is characterized by very low activity, thus the overall power consumption is greatly reduced if compared to other solutions, such as Convolutional Neural Networks. To enhance the computing capability of an IoT device during the execution of SNN based algorithms, the thesis describes the design of an interfacing solution for controlling a reconfigurable SNN-accelerated coprocessor, named ODIN, by means of a RISC-V based System on Chip (SoC), without any remote controller from the cloud. The designed architecture exploits the serial peripheral interface (SPI) to let the RISC-V core configure the accelerator parameters, thus offloading the SNN task on ODIN. The capability of the system to work as a standalone device has been validated by configuring a synfire chain simulation without the intervention of an host computer. A synfire chain is a particular arrangement of spiking neurons, which are connected in a loop, firing in series once a proper input stimuli is provided. The synfire chain has been used to benchmark the proposed architecture because of its predictable behaviour, which can be monitored through Register Transfer Level (RTL) simulation. The network behaviour is tested on a few case scenarios, where a number of parameters are changed, and the results are matched against the expected ones. Thus, demonstrating that the proposed solution could avoid the usage of a host computer to control and configure the SNN based accelerator.

Relators: Gianvito Urgese, Evelina Forno
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 93
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/18187
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