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In-depth power optimization of Advanced Arm CPU

Andrea Trufini

In-depth power optimization of Advanced Arm CPU.

Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021


The technology revolution of the last decades has been conducted by the introduction and evolution of Integrated Circuit (IC) which allowed the realization of the hi-tech devices today used all over the world. Starting from the 60s the IC technology has gone from the Small Scale Integration (SSI), which consists in the integration of few transistors, to the Super Large Scale Integration (SLSI) based on the use of billions of transistors through a few nanometers CMOS process. The increase of the number of transistors correlated by the decrease of the technology process dimensions has gone through the evolution in tandem with the increasing complexity of IC, going from very simple logic circuits to high-complexity System On a Chip (SoC). The modern CPUs undergo a physical implementation process for the translation of a RTL design into a physical layout usable by the silicon foundries. One of the main aims of companies like ARM is to find the best Power-Performance-Area (PPA) trade-off in a design. Thus, for the development of next generation CPUs it could be very useful to find new ways to provide accurate data in a faster manner, helping the energy efficient processors design keeping up with progress, competition and business, where the time factor is crucial. This document is based on the exploration of the Physical Implementation Flow of ARM: the first part focuses on the identification, analysis and comparison of different flow stages with the aim of performing data prediction, the second one is based on the development of a tool for specific data extraction (such as power, switching activity and capacitance) on a set of predefined design modules and, in conclusion, a real test case which involves the use of the developed tool to reach a power optimization is described.

Relators: Luciano Lavagno
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 76
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: TELECOM ParisTech - EURECOM (FRANCIA)
Aziende collaboratrici: ARM France SAS
URI: http://webthesis.biblio.polito.it/id/eprint/17934
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