Pierpaolo Mori'
Winograd aware Quantized Neural Network accelerator design.
Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020
Abstract
Convolutional Neural Networks (CNNs) are widely used in several application fields such as image processing, computer vision and speech recognition. Their high accuracy is obtained at a cost of a huge amount of parameters and so an high memory demand and number of MAC operations. Hardware accelerator are required in order to speed up the inference. Even if GPUs are the main hardware accelerator platforms because of their huge computation capabilities, they are power-greedy devices, not suitable for embedded and mobile applications, where the computational, memory and power resources are limited. Therefore, FPGA based accelerators can be considered which can offer the right trade-off between performance and flexibility limiting the power consumption.
Quantization and Tiling techniques can be exploited to reduce the complexity of MACs and to limit the SRAM and DRAM requirements respectively, bringing benefits in energy consumption and/or throughput
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