Gabriele Mario Caddeo
Flexible On-Chip Networks for Dynamic Dataflows on Convolutional Neural Network Accelerators.
Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020
Abstract
Convolutional Neural Networks (CNNs) have become the state of the art for many computer vision tasks. Their highly parallel computation graph structure offers many possibilities for optimization of hardware. While the precision and the accuracy of state-of-the-art CNN are remarkable, the deriving computational complexity and significant amount of data movement pose a challenge in terms of energy efficiency. Focussing on moving the computational complexity off-chip and reducing the off-chip↔on-chip communication shows successful results in terms of energy efficiency and throughput. Due to the deterministic nature of CNN execution, the communication does not necessarily require complex routing algorithms typically supported by Network-on-Chips (NoCs).
A light and efficient on-chip interconnection can be created to support broadcast, multicast and unicast transfers between the memory and the processing elements
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