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Hardware support for a novel variable precision floating point format in a scientific computing environment.

Riccardo Alidori

Hardware support for a novel variable precision floating point format in a scientific computing environment.

Rel. Andrea Calimera, Andrea Bocco. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020


Most modern computing systems rely on standard IEEE 754 hardware for Floating- Point (FP) operations. This approximate representation of real numbers is affected by round-off errors such as cancellation and absorption. The accumulation of these errors may lead to completely inaccurate results. One way to solve this problem is to increase the precision of the data in memory by using Variable-Precision (VP) formats. The VP formats existing in the State of the Art (SoA) are UNUM, Posit and the “IEEE-Like” category. The aim of this work is to compare VP FP formats, evaluating which of them minimizes both computational error and execution latency. Besides the SoA, three additional formats are proposed in this work: Custom Posit, Not Contiguous Posit and Modified Posit. This work is implemented in a RISC-V environment. This architecture supports two different variable length FP formats: the internal one (with 64 bit granularity in precision) and the UNUM used as VP FP memory format (with an 8 bit bit-length granularity). The conversion among these two formats is done through dedicated hardware units placed inside a dedicated Load and Store Unit (LSU). With the aim to properly evaluate the VP formats mentioned above, the existing LSU is expanded to support five additional VP FP formats with variable bit-length in memory. The 65nm ASIC synthesis estimated an LSU area of 0.42mm 2 and a power consumption of about 0.96mW. The areas of all the designed hardware conversion blocks are comparable. UNUM converters are in average 40% bigger than the others. The full architecture is FPGA integrated to speedup the system benchmark. The performance of the VP formats are evaluated with the Gaussian Elimination (GE) linear solver. Multiple experiments are performed running the GE over each format varying all its parameters. Experiments show that it is possible to minimize the error of a format by decreasing the exponent bit-length. In addition, VP formats allow to decrease the computational error, independently on the one used to represent numbers in memory, gaining up to 63 additional decimal digits of accuracy compared with the legacy IEEE 754 FP format. The application execution latency is not affected by the VP FP memory format, but it depends on the FP data bit-length and the internal precision: for example, the IEEE-Like is the simplest format, but it shows the same latency as the Custom Posit. The IEEE 754 double is always the fastest, thanks to its dedicated fixed-precision hardware. UNUM is the worst among the VP FP formats, for both the precision and algorithm latency. This work shows that Posit is 16.7% slower than the others. As a conclusion the application and dataset under analysis show comparable results to each VP FP format, except for UNUM and Posit. The fact that the VP formats are comparable implies that there is none of them that is absolutely better than the others.

Relators: Andrea Calimera, Andrea Bocco
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 79
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: CEA-Leti (FRANCIA)
Aziende collaboratrici: CEA - LETI
URI: http://webthesis.biblio.polito.it/id/eprint/16057
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