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VLSI architecture of a low-complexity Wiener Filter for video coding

Giorgio Armanno

VLSI architecture of a low-complexity Wiener Filter for video coding.

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020

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The aim of presented thesis work is to provide a special purpose hardware implementation of AOMedia AV1 Wiener Filter. The basic idea was to start from the analisys of the entire AV1 codec and then focus on a very specific part based on the profiling results of the codec, in order to understand the usage percentage of each one and evaluate which one needed of more attention. The work presented here concerns the design, the implementation, the analysis and a possible optimization of an Hardware architecture for the Wiener Filter of AV1. The reasons why the attention was focused on the Wiener filter are multiple: first of all, the lack of informations on this kind of process in literature. Moreover, the importance of the in-loop filters in AV1 codec mechanism of enhance the quality of the output images and, finally, the considerations about its usage in the coding process that will be better explained in thesis development. The first attempt to implement the architecture was to try to start from the source C code (available on AOMedia Website using GitHub) and build an equivalent model based on matrix calculation. This approach has been left because of many drawbacks related to the size of involved data that will be explained during the following chapters. So the choice was to follow completely the C code to maintain a behaviour coherency : the basic implementation derives from an algorithm to architecture mapping from the Wiener Filter C version in terms of data, operations, parallelism. The basic idea of the presented work is not only to show the steps and the design choices to obtain a working VLSI implementation starting from some binding inputs, but also how it is possible to improve it based on the application to develop. So, once obtained a working architecture, it has been synthesized with Synopsys to evaluate the critical points and understand the direction to follow to improve that performances. Due to the huge dimension of many internal component of the filter and the very high parallelism, the complexity has been considered like one of the most critical parameter to optimize. Starting from the basic implementation and by using deeply a folding approach on the bigger component inside the architecture, a "low-complexity" version has been implemented, obtaining an area reduction of about 90%.

Relators: Maurizio Martina
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 98
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/15933
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