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Next Generation Hardware Acceleration opportunities in Data Centers

Giuseppe Dongiovanni Mancino

Next Generation Hardware Acceleration opportunities in Data Centers.

Rel. Maurizio Martina, Alberto Dassatti. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020

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The world has entered in the Era of Data. The role of data centers is more and more relevant due to the increased amount of data produced that have to be computed and stored. Therefore the scientific and engineering interest focuses on the research of new technologies to increase the computational power and storage capacity of data centers, and at the same time on the necessity to reduce their energy footprint. Some of the available technological solutions, that can be used to meet the requirements for performance and energy efficiency, are presented in the first part of this thesis. They are the well-established NVMe protocol, designed to become an industrial standard that exploits the performance given by the PCIe it leverages, and the computational storage. The combination of these two technologies is the enabler framework for the near data computational paradigm also known as smart storage. The idea is simple: move the computing close to the data reducing the data movement, main source of energy dissipation, without compromising in processing performance. Then the attention is focused on the development of a computational storage based on the NVMe protocol: the prototype is built on a Xilinx FPGA board, on the basis of an open-source project of a NVMe SSD controller. The created prototype represents a scalable and standard compliant solution: it has been developed to experience and explore the capabilities of the used technologies and standard, and the possible benefits that they can provide to data centers. Extensive benchmark tests have been carried out to characterize the device and discover its performance limits, in terms of both data rate and latency. At the same time, a general test application has been integrated in the prototype to evaluate, as real-world example, the complexity that the deployment of hardware accelerators involves.

Relators: Maurizio Martina, Alberto Dassatti
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 69
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: Haute Ecole d'Ingénierie et de Gestion du Canton de Vaud (HEIG-VD) (SVIZZERA)
Aziende collaboratrici: HEIG-VD
URI: http://webthesis.biblio.polito.it/id/eprint/15267
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