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Low latency bus-based solution for inter-processor communication

Giuseppe Carnicelli

Low latency bus-based solution for inter-processor communication.

Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020


Digital electronic devices, like smartphones, smartwatches, video game consoles typically contain one or more System on Chip (SoC) that are composed by many components such as processors, memories, control units. The increasing demand of data processing increased the number of processors that communicate in a SoC, so the complexity problem is becoming important.\\ Components on a SoC are connected through an on-chip communication architecture. Different SoC communications have a different impact on the performances, power consumption, cost, design time, area and latency. For example, today a smartphone can contain many different sensors like GPS, more than one camera, gyroscope, accelerometer etc.).\\ Moreover, with the spread of the new 5g protocol communication, the Internet of Things (IoT) field and the automotive fields are exploding with an increasing number of sensor connected in networks that are in charge to exchange data in a real time domain. A critical parameter is the data latency and it is due to the high demand of embedded sensors in a specific device. For example, in the gaming field, to have a a very responsive experience with the increasing of the frame-rates images processing and the high resolution, the GPU needs to exchange data with DSP and memory in a very fast way. In the automotive field, the increasing of sensor fusion systems and real time Advanced driver-assistance systems (ADAS), that are electronic systems that help the vehicle driver while driving or during parking, the number of connected sensors in a car is increased a lot to have very accurate data.\\ This thesis faces the latency with different on-chip communication architectures for Inter-processor communication and presents a possible bus-based design solution which has benefits in terms of latency.\\ In the first chapter today's problems, related to the increasing of processors in SoC, are stated. Then, the state of art of interprocessor communication is shown by explaining two different data communication approaches: bus-based architecture and Network-on-Chip (NoC) architectures that are an emerging solution for multiprocessors architectures.\\ The second chapter is focused on the Standard On-Chip Bus-Based Communication Protocols that are most commonly used such as the Advanced Microcontroller Bus Architecture (AMBA) family and the IBM Core Connect family.\\ In the third chapter the most commonly NoC router architectures used are shown to have an overview on the most important NoC router algorithms.\\ The fourth chapter describes the proposed bus-based design solution focusing on design choices and describing I/O interfaces and features.\\ The fifth Chapter shows the results in terms of area and latency of the proposed solution in order to prove its benefits by comparing its performances with a Mesh and NoC solutions that are the today's most commonly used architectures.\\ Moreover, future developments are presented to improve and add more features on the proposed bus-based design solution.

Relators: Guido Masera
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 65
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: QT Technologies Ireland Limited (IRLANDA)
Aziende collaboratrici: QT Technologies Ireland Limited
URI: http://webthesis.biblio.polito.it/id/eprint/15265
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