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Low-latency implementation for inter-process communication

Alessio Parisi

Low-latency implementation for inter-process communication.

Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020


With the increasing capabilities that the latest 5G technologies enable, the demand for multiple data sources integration is exploding. More processors are added in every new generation device, with the need of managing the streams of data generated by an increasing number of sensors. This requirement results in having a solution for fast, low latency inter-process communication. Moreover, given the exponential growth of the number of sensors and processors, this solution needs to be highly scalable. Latency is critical in inter-process communication because it enhances the responsivity of the whole system, enabling the use of new types of sensors for new use cases. For example, in virtual reality (VR) applications, low latency communication between the motion sensors and the Graphics Processing Unit (GPU) is needed to reduce the motion sickness that the user can experience. Moreover, new sensors for eye tracking can be used to lower the workload of the GPU, elaborating in high definition only the part of the scene in the field of vision of the user. Also, in automotive applications, the processing elements have to analyse data coming from numerous sensors at the same time to generate an accurate outcome. The smaller the time passing between the detection of an obstacle and the elaboration, the safer the system becomes, increasing the margins for reaction. Furthermore, the higher the number of sensors, the more accurate the decision is. In this study, the critical parameters for inter-process communication are first analysed, talking about the importance of low latency and scalability, with an overview on the features that an improvement of these can enable. Then the state of the art of the actual solutions are presented. First the use of Network On a Chip (NOC) is considered, then more expensive solutions, in terms of area and power, like dedicate BUSes are analysed, and finally software solutions are contemplated. In the second part of this work, an improvement to the current implementations is presented, in terms of latency, area and scalability. The proposed microarchitecture is designed to improve on scalability with respect to the dedicated BUSes solution, greatly decreasing the latency with respect to the NOC solution. Finally, the proposed microarchitecture is compared with the state of the art of the actual solution to extrapolate the performance improvement.

Relators: Guido Masera
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 71
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: QT Technologies Ireland Limited (IRLANDA)
Aziende collaboratrici: QT Technologies Ireland Limited
URI: http://webthesis.biblio.polito.it/id/eprint/14455
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