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Optimization of Neural Networks on Microcontrollers

Simone Antonio Iammarino

Optimization of Neural Networks on Microcontrollers.

Rel. Andrea Calimera, Valentino Peluso. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020


This paper aims to provide an automatic tool that embeds the knowledge required to design hardware-aware neural networks to allows their implementation on microcontrollers. An algorithm called AUTONET is developed, which, given an input dataset and memory constraints of the target hardware, and aided by network design rules, generates autonomously an over-parameterized network intrinsically optimized for memory, to be used as the search space within a differential type NAS. The search space found by AUTONET on CIFAR10 and CIFAR100 datasets generates networks that are on average 95% smaller and 68% faster with respect to the ones found using MobileNetV2 as a backbone, being able also to compete in the Visual Wake Word dataset challenge obtaining an accuracy of 86.47%. In conclusion, this study demonstrates that NAS can be further generalized taking into account the overall architecture of the network from which start to search, incorporating the memory constraints directly in the search space in order to find small and accurate neural networks that can be deployed on IoT devices.

Relators: Andrea Calimera, Valentino Peluso
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 68
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/14439
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