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PPA analysis on a processor IP for next-generation functional safety SoCs

Giulio Roggero

PPA analysis on a processor IP for next-generation functional safety SoCs.

Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020


In this thesis, it will be described what is a PPA analysis and how it is possible to perform it, starting from introducing the investigated parameters and the basic information required. Subsequently, it will be explained how to integrate a third party IP core in Qualcomm's flow together with other components and enable the synthesis. Having generated gate-level netlist, the results obtained with one of the most recent technology nodes will be reported and they will be compared with each other. The synthesis runs will be run integrating Qualcomm's component in a different way, and thus the netlist will present significant variations. Those differences will be the target of the analysis. Also, runs involving different corners will be used to identify which components are more sensitive to variations. Then, the causes of such differences will be investigated and a reasonable explanation for the obtained numbers will be given, therefore pointing out the most desirable solution for the design analysed and the reasons behind it.

Relators: Luciano Lavagno
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 86
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: TELECOM ParisTech - EURECOM (FRANCIA)
Aziende collaboratrici: QT Technologies Ireland Limited
URI: http://webthesis.biblio.polito.it/id/eprint/14379
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