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SoC Silicon Validation: possible approaches and practical results

Simone Alessandro Chiaberto

SoC Silicon Validation: possible approaches and practical results.

Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020


The internship project consists of two main parallel objectives: as first, analyzing the performances of a set of IPs (Intellectual Properties) components (Ethernet, DDR RAMs, SDIO) available on the new under-development SoC by NXP®, the i.MX8DXL. Those performances are specifically related to the type of the peripheral, and are obtained thanks to a remote FPGA-based SoC simulation environment, called ZeBu® and provided by Synopsys®. On top of this, as a second but equally important goal, tests are run both bare-metal and through the usage of a real-time OS, called FreeRTOS™, whose advanced and widespread capabilities may play a crucial role in raising the silicon validation activity on a different perspective. This duality has been then analyzed, for the sake of the study, to determine if and which one of the two approaches overcome the other in terms of features provided. As a last aspect, along the ZeBu® simulation support, a physical sample of a similar SoC mounted on board, the NXP® i.MX8QXP, is available to act as a real-world reference. This opens up to further comparisons and analysis about different possible solutions available for the validation activity (distinguishing the pre-silicon validation needs from the post-silicon ones) and about the accuracy of the ZeBu® simulation environment mentioned before. The i.MX8QXP physical SoC has been used instead of the i.MX8DXL one since the latter won’t be produced before this document is published. Except for some corner cases, the raw performances obtained, for all the IPs, are compliant with the initial specifications, as defined by the respective standard, compatibly with the available hardware. The usage of the FreeRTOS™ in testing and bench-marking helped to get closer to the application level at which customers will, eventually, employ the SoC, adding a true value to the pre-silicon activity, as well as speeding-up the first stages of the post-silicon one. Finally, despite some drawbacks spotted in using Synopsys® ZeBu®, the results showed to be pretty consistent with the real-word reference.

Relators: Luciano Lavagno
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 111
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: TELECOM ParisTech - EURECOM (FRANCIA)
Aziende collaboratrici: NXP Semiconductors France SAS
URI: http://webthesis.biblio.polito.it/id/eprint/14357
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