State-of-the art Convolutional Neural Networks (CNNs) can perform tasks such as image classification or voice recognition with high precision, at the expense of high computational complexity and energy requirements. Making a design focused only on a single aspect could result in a system which is unable to satisfy energy or latency requirements, critical in several applications such as autonomous driving. This emphasizes the need for taking both the hardware specific requirements into consideration for a given application scenario. For highly-parallel processor architectures, this work provides two methods of design space exploration in the context of task-to-processor mapping, aiming to find the optimal resource binding strategy for a given network and hardware architecture, in a reasonable time.