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Design of the frontend for LEN5, a RISC-V Out-of-Order processor

Marco Andorno

Design of the frontend for LEN5, a RISC-V Out-of-Order processor.

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019

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Abstract:

Progetto di un core RISC-V out-of-order

Relators: Maurizio Martina
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 101
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/13198
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