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Sub-threshold design of arithmetic circuits: when serial might overcome parallel architectures.

Simone Fini

Sub-threshold design of arithmetic circuits: when serial might overcome parallel architectures.

Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019

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Abstract:
Relators: Luciano Lavagno
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 96
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: Norges Teknisk-Naturvitenskapelige Universitet (NTNU) (NORVEGIA)
Aziende collaboratrici: Norwegian University of Science and Tech
URI: http://webthesis.biblio.polito.it/id/eprint/12534
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