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Hardware and Software Design for Automatic Resistance Characterization

Loris D'Amico

Hardware and Software Design for Automatic Resistance Characterization.

Rel. Marcello Chiaberge. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019


The purpose of this thesis is to realize a circuit able to characterize Spea’s resistance measurement systems and calibrate it. Since the company’s systems must also be able to measure inside an IC, parallel programmable capacitances are placed in the final PCB. To achieve the goal, the thesis design will only cover the range 10Ωto 650 kΩin parallel to 1 nF, 10 nF, 100 nF,440 nF. In the first chapter, an introduction on measurement is given, with all the needed definitions and general rules to compute uncertainty and other statistical variables related to the measurement. In the second chapter, the board is designed. To do this all the steps are studied: 1. Evaluation of already designed instruments; 2. Schematic design; 3. Missing component selection (based on component value, tolerance and temperature coefficients, availability in the warehouse, price, etc); 4. The interface needed and circuit compatibility evaluation; 5. PCB design. In this prototype phase, two boards are used: a USB - SPI board converter and the designed resistance board. In the third chapter, the software is designed with C++ language as follows: 1. Read from .ini file global variables (number of DUT TP, number of measures to be done, test model identification, capacitance range in parallel); 2. Read from .csv file all the parameters required to measure; 3. Read from EEPROM the actual resistances values mounted on the PCB; 4. Program the board to obtain the required resistance and capacitance to be measured; 5. Measure multiple times and compute all the statistical variables;6. Write a new .csv file with the results and the parameters used to measure.

Relators: Marcello Chiaberge
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 89
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Spea SpA
URI: http://webthesis.biblio.polito.it/id/eprint/12529
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