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Developement of RISC V based System Controller for Coarse Grain Reconfigurable Architecture

Riccardo Cappai

Developement of RISC V based System Controller for Coarse Grain Reconfigurable Architecture.

Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019

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As of 2019, RISC-V Instruction Set is drawing more and more attention among companies and academia. Due to the fact of being easy to use and not proprietary, it allows developers to create cheaper designs without the limitation of proprietary Instruction Set Architecture (ISA), enabling even faster innovations. The Instruction Set is composed of a very basic one and a lot of independent addable extensions, allowing developers to customize the ISA in order to fit their needs. At the same time, the ASIC industry is struggling to adapt its methods to always larger designs. The introduction of standard cells allowed a decrease in design complexity, but since then the designs grew from a complexity of O(10K) gates to O(10/100M) gates. In this thesis work, a design of a RISC-V processor is made adaptable to the SiLago design methodology, developed by KTH university with the goal of adapting the present needs of the VLSI community. On top of that, a new algorithm for an adaptable Network on Chip is proposed. The RISC-V component and the Network on Chip router have been designed down to their GDSII files following the SiLago flow.

Relators: Luciano Lavagno
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 107
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: KTH - Kungl. Tekniska Högskolan (Royal Institute of Technology) (SVEZIA)
Aziende collaboratrici: KTH Royal Institute of Technology
URI: http://webthesis.biblio.polito.it/id/eprint/12525
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