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Evaluating basic building blocks needed to build FPGA fabrics from memristors.

Francesco Franco

Evaluating basic building blocks needed to build FPGA fabrics from memristors.

Rel. Luciano Lavagno, Dirk Koch. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019


Nowadays, semiconductor industries are facing difficulty to follow Moore's law, which predicts that the numbers of transistors are doubled every 18 months. The primary benefits were an increment of the performance and a reduction of the cost per transistor. However, CMOS scaling is encountering problems to shrink devices below 28 nm, because the cost per transistor is no longer decreasing. Moreover, the performance boost that was guaranteed from the scaling process has essentially stopped for about a decade. Nevertheless, the need for computational power is increasing. Currently, the computational demands are grown in application fields such as machine learning and bio-inspired computer. These require massively parallel computation and may adopt FPGA accelerators. New technologies try to address both challenges, providing scalability beyond CMOS and increasing computational performance. Among these, memristor technologies are the most promising. Memristors combined with CMOS processes can increase computational power while further extending Moore's law. Memristors are nanoscale devices that show promising qualities. They are scalable, non-volatile, compatible with CMOS process. Moreover, a memristor can store more states which can be translated into binary values. These properties make memristor devices the favourite candidates for high-density memories, neuromorphic computing, programmable analogue circuits and reconfigurable architectures. However, many challenges should be tackled to introduce memristive technologies into electronic systems based on these new devices. In the project, design challenges are analysed. In particular, in this work we discuss memristor models and how memristive devices can be interfaced with CMOS circuits. Memristor models are reviewed and examined because they are fundamental to enabling the design of electronic circuits. Memristor models reduce the complexity for designers that should not worry about tangled details of their functionality. Furthermore, we examine how memristors are interfaced with a reconfigurable architecture. This is a step toward the realisation of FPGAs enhanced by means of memristors. In particular, readout circuits are investigated. These circuits translate the memristor state into binary values. A completely novel readout circuit has been introduced. The proposed reading solution converts the memristor state into a digital form without using power-hungry resources, such as operational amplifiers and current/voltage references. Hence, readout circuits that drastically improve power and reading time beyond the state of the art can address the interface challenges of the memristor in reconfigurable architectures.

Relators: Luciano Lavagno, Dirk Koch
Academic year: 2018/19
Publication type: Electronic
Number of Pages: 96
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: The University of Manchester, School of Computer Science (REGNO UNITO)
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/11686
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