Functional verification has long been a major concern in digital design. Over the years, the huge investment in verification spurred the development of tools and methodologies for systematic and cost-effective solutions. In particular, the verification environment covers a fundamental role in the process since it collects the results of the tests to extract more valuable information about the verification closure of the design. The proposed flow is based on vManager tool of Cadence and supports all the phases of the System-On-Chip (SoC) verification process from the functional test up to the RTL freeze and final Tape-Out. The new methodology is designed to be a complementary module for the current verification environment, to cover those flaws still affecting the verification process.