To leverage data-level parallelism at the instruction level, algorithms for signal processing like the Fast Fourier Transform have been implemented using SIMD extensions. For the Arm processor family, the SIMD instructions are part of the NEON architecture extension. The introduction of the Scalable Vector Extension (SVE) in the Armv8-A architecture has significantly enhanced the vector processing capabilities. The next generation is coming and it will be known as SVE2. One of the key area for Arm is the speedup of the networking architectures at the physical layer. Thus, in this thesis the implementation and the performance of algorithms that utilize the three Arm's vector extensions have been investigated.