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Thesis by Valente, Luca

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Thesis

Luca Valente. A Vector Processing Unit implementation for RISC-V Vector Extension: Functional Verification and Assertions on submodules. Rel. Luciano Lavagno. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020

This list was generated on Fri May 17 05:34:09 2024 CEST.

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