Area and power impact of different clock controller design strategies based on clock domain crossing analysis

Design and Analysis of clock controller architectures. Three clock controller for Sistem on Chip application has been designed with different design strategies. The three clock controllers has been inserted inside a subsystem of the Qualcomm Snapdragon chip dedicated to sensor's interfacing. The three design has been synthesized and the difference between them has been studied. Finally, one of the three synthesized structure has been analyzed from the timing point of view to verify its correctness. In the very last part, thanks to a developed tcl cript, the clock domain crossing of the subsystem has been investigated and, relying on it and on the synthesis outcome, a new clock controller structure has been proposed.