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Real Time Packet Processing with FPGAs: A network security toolbox with encryption features designed for FPGA logic-fabrics

Matteo Collura

Real Time Packet Processing with FPGAs: A network security toolbox with encryption features designed for FPGA logic-fabrics.

Rel. Luciano Scaltrito, Sergio Ferrero, Angelo Geraci. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2018

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Abstract:

The goal of this Thesis is to design an application based on a Field Programmable Gate Array (FPGA) architecture, for security purposes. Such application consists in real-time processing the network packets exchanged across a wired Ethernet connection. This allows to filter the exchanged data according to a specific set of conditions, programmed by the user. Moreover, in order to guarantee a secure communication between two peers, it should also include an encryption scheme, to manage encryption/decryption of data in real time. As a result, this application is referred to as a toolbox, due to the different options of configuration. The device used for this purpose is an hybrid solution, defined as System on (Programmable) Chip (SoC), that embeds a classic CPU architecture into a FPGA logic-fabric. As a result, depending on the implemented resource balance, three different strategies were followed to achieve the goals of this Thesis, but only one fully succeeded. This last attempt managed to achieve all the goals, with a design started from scratches. All the three designs will be explained thoroughly, indicating the reasons of failure or success compared to the achieved results. In the end, an overview on the future upgrades will be provided, stimulating the reader curiosity on such an interesting topic as security.

Relatori: Luciano Scaltrito, Sergio Ferrero, Angelo Geraci
Anno accademico: 2018/19
Tipo di pubblicazione: Elettronica
Numero di pagine: 148
Soggetti:
Corso di laurea: Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Ente in cotutela: Knowledge Resources, GmbH (SVIZZERA)
Aziende collaboratrici: Knowledge Resources GmbH
URI: http://webthesis.biblio.polito.it/id/eprint/8485
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