polito.it
Politecnico di Torino (logo)

Die Attach Process Optimisation for System-in-Package modules

Paolo Piquereddu

Die Attach Process Optimisation for System-in-Package modules.

Rel. Luciano Scaltrito, Valentina Bertana. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2025

[img]
Preview
PDF (Tesi_di_laurea) - Tesi
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (1MB) | Preview
Abstract:

The evolution of electronic packaging has progressed through distinct technological phases, each addressing the increasing demands for miniaturization and performance. Starting from traditional printed circuit board (PCB) technology, to multi-chip-modules (MCM) to more modern technologies such as system-on-a-chip (SoC), System in a package (SiP) and Heterogenous Integration (HI) however what has not changed is the need to create stable connections between devices and substrates and the different die attach processes are what enables these advanced packaging approaches. The selection of appropriate die attach materials and methods directly impacts device performance, reliability, and manufacturability of an entire system or device. Therefore for consumer applications the die attach is essential for everything ranging from smartphones, smart-appliances, wearables to Internet of Things (IoT) sensors where thermal mangment and miniaturization are critical. Similarly for High Performance Computing and Data Centers, Medical and Health sector, Aerospace, Defense and Automotive sector are required die attach materials capable of surviving harsh environmental conditions and extended operational lifetimes while, particularly in power electronics and high-frequency devices, are necessary solutions that can withstand extreme operating conditions while maintaining electrical and thermal performances since the attach material is the first point of contact with the device and its predominant path for heat dissipation in the majority of packaging geometries for semiconductors applications. Choosing the most suitable die-attach method is essential and the possibilities are many depending on what parameters and properties are deemed more important for the desired application. In this thesis will be first presented some the most commonly used techniques for establishing stable physical, thermal, and electrical connections, among them will be discussed Adhesive die attach, Eutectic die attach, Sintering and Cu-Cu hybrid bonding while for the Soldering process there will be a deeper dive into its elements, regulations, materials and with the trial of optimization of a reflow profile for two different solder pastes (SAC305 and Sn57Bi42Ag1) initially by attaching a die onto a DBC-like substrate (created by depositing a Copper layer over a Titanium layer for adhesion on an alumina substrate) then onto real DBCs and characterizing the resulting solders by means of a Shear Test. The Soldering was done in an Infrared reflow oven, in order to match the temperatures inside the oven with the ones recommended in the data sheets of the twopastes, were employed both an external pt1000 thermoresistor and a thermocouple read by the oven itself. After these initial reflow profiles were found I optimized them in order to reduce visible defects such as flux residue, solder balling and dull appearance of the solder. For a visual analysis of the results were used SEM imaging and optical imaging (DSX1000). For testing the adhesion strength of the soldering layer, a specific set up has been developed to perform a shear test, using additive manufacturing technology. For the Sn57Bi42Ag1 solder paste I was able to obtain visually clean and shiny solders while for the SAC305 I was not able to obtain satisfying results for similar paste volumes. During the shear test on the dbc-like the copper layer was peeling off before the solder broke while for the dbc the result were comparable values found in literature.

Relatori: Luciano Scaltrito, Valentina Bertana
Anno accademico: 2025/26
Tipo di pubblicazione: Elettronica
Numero di pagine: 81
Soggetti:
Corso di laurea: Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: NON SPECIFICATO
URI: http://webthesis.biblio.polito.it/id/eprint/38786
Modifica (riservato agli operatori) Modifica (riservato agli operatori)