Implementation of intermittent-robust computing on RISC-V architecture. RISE: RISC-V Intermittent System Extensions for Batteryless IoT Devices

The growing deployment of batteryless Internet of Things (IoT) devices powered by ambient energy harvesting highlights the need for architectures capable of sustaining correct and reliable execution under frequent and unpredictable power interruptions. This thesis addresses this challenge by proposing RISE (RISC-V Intermittent System Extensions), an architectural and ISA-level framework that enables intermittent computing on a pipelined RISC-V processor. The proposed approach introduces four lightweight hardware modules: the Intermittent Computing Register Wrapper (ICRW), which encapsulates the processor state and tracks modifications through dirty-bit management; the Power Control Unit (PCU), which performs selective background backups of modified registers; the Restore Control Unit (RCU), which reloads saved state upon power resumption; and the Dispatcher, which transparently arbitrates memory bus usage between normal execution and backup transfers. In addition, the instruction set architecture is extended with the .ICA primitive, which allows programmers to define atomic code regions that guarantee correctness and consistency despite intermittent power supply. RISE is designed to preserve compatibility with standard RV32I pipelines, requiring only minimal modifications to the decode stage, while maintaining full portability across different RISC-V cores. The framework avoids reliance on non-volatile elements within the processor itself, ensuring CMOS compatibility and scalability. Backup and restore operations are executed concurrently with regular computation, thereby minimizing performance and energy overhead. The framework was implemented in Verilog HDL and evaluated through simulation and synthesis using the Xilinx Vivado-2024.1 toolchain. Experimental results demonstrate that the proposed architecture achieves efficient and reliable execution in intermittent environments. In benchmark workloads, a complete processor state backup requires on average 203 cycles (0.203 µs at 1 GHz), confirming that RISE provides a practical and effective solution for sustainable intermittent computing in energy-harvesting IoT systems.