Alternative Store Buffers

Modern high-performance Out-of-Order processors rely heavily on Store-To-Load Forwarding to reduce load latency, placing significant timing pressure on the Store Buffer as the instruction window scales. The associative search logic in the Store Buffer, essential for identifying forwarding candidates, becomes a critical bottleneck, creating a scalability wall for larger designs. This thesis proposes and evaluates a Hierarchical Store Buffer as a solution to this challenge. This design decouples the Store Buffer’s functions by splitting it into two specialized structures: a Hazarding Store Buffer, which maintains all in-flight stores for precise hazard detection, and a smaller Forwarding Store Buffer, which mirrors a sliding window of recent stores to enable fast, low-latency Store-To-Load Forwarding. This separation is motivated by the key observation that most forwarding events occur over short distances in program order, allowing a compact Forwarding Store Buffer to capture the majority of performance benefits. The work proceeds through a two-phase methodology. First, a cycle-approximate model explores the design space, confirming that a small Forwarding Store Buffer can achieve near-optimal performance with limited hardware overhead. Subsequently, a Register-Transfer Level implementation is developed, validating functional correctness and providing initial physical design insights. Results indicate that the hierarchical approach is functionally sound and can preserve most Store-To-Load Forwarding performance. However, the developed prototype reveals higher-than-expected Instructions per Cycle degradation and significant timing violations, underscoring the complexity of balancing performance, area, and timing. The thesis concludes by identifying future optimization opportunities, including alternative internal organizations to the Forwarding Store Buffer and enhanced alignment support, to bridge the gap between architectural promise and practical implementation.