ADC Design for Bit-serial Input Encoding in PCMBased Array Analog Hardware Accelerator

This work presents the design and simulation of a sensing circuit for an analog Phase Change Memory based Multiply and Accumulate Hardware accelerator, with a focus on current transfer linearity and sensitivity. The goal was to accurately transcribe the output current of the array into a voltage ready for digitization, while mitigating non-ideal effects such as channel length modulation and process variation. A two-stage current mirror architecture was developed: the first stage offers tunability to adapt the charging range, and the second stage, operating in a calibration context, corrects for process induced mirror mismatch. Simulation results confirm that this architecture improves sensitivity and reduces non-linearity (S2 < 1% for around 50% of the simulated cases), allowing for better utilization of the ADC dynamic range. The stacked transistors with different threshold voltage types (rvt/slvt) were also shown to significantly limit output voltage dependence. While promising, further modelling of mirror non-idealities is necessary for accurate full-chip prediction. This work contributes a crucial step towards reliable, high-accuracy analog-to-digital conversion in neuromorphic systems.