Niccolo' Ervaz
Investigation of novel on-chip signal processing techniques.
Rel. Carlo Ricciardi. Politecnico di Torino, NON SPECIFICATO, 2025
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Accesso riservato a: Solo utenti staff fino al 24 Ottobre 2028 (data di embargo). Licenza: Creative Commons Attribution Non-commercial No Derivatives. Download (5MB) |
| Abstract: |
This thesis investigates unconventional approaches to analog-to-digital conversion and on-chip signal generation, focusing on both the opportunities and the inherent limitations of architectures that deviate from mainstream solutions. The first part of the work is dedicated to the study of an ADC based on the Hopfield neural network model. A transistor-level implementation using resistive networks was developed, which revealed several critical challenges. In particular, the binary-weighted resistors result in a large time constant, necessitating sizable buffers to drive the resistive network. This introduces additional area and power overheads, while also making the circuit sensitive to kickback and requiring precise settling to maintain accuracy. Despite these limitations, alternative device technologies, such as memristors, could offer more compact and efficient implementations, making this architecture potentially attractive in emerging technology nodes. Building on this foundation, the Hopfield concept was extended to a capacitive implementation, which shows strong similarities to charge-sharing ADC architectures. While this approach mitigates some of the limitations of resistive designs, it introduces its own set of challenges. The input signal undergoes attenuation, and the architecture is sensitive to comparator offsets, resulting in reduced linearity compared to a conventional charge-redistribution SAR ADC. Additionally, there is no straightforward way to reduce the total capacitance as is possible in SAR architectures, limiting scalability. Nevertheless, a key advantage of this design is the absence of a fast on-chip buffer, which can simplify integration and reduce power consumption in some contexts. The second part of the thesis focuses on the design of an on-chip sinewave generator targeting the low-to-mid frequency range, relevant for communication, biomedical, and mixed-signal testing applications. The proposed generator leverages harmonic cancellation techniques to achieve extremely high spectral purity, with a total harmonic distortion (THD) close to –100 dB. An initial mixed-signal implementation successfully combined analog accuracy with digital programmability to meet stringent performance targets. Finally, the work explores a transition toward a more digital-oriented design, aiming to simplify circuit complexity, enhance scalability, and improve portability across technologies while preserving spectral purity. Overall, the thesis provides a comprehensive analysis of both neural inspired ADCs and harmonic-cancellation-based signal generators, highlighting the trade-offs, practical limitations, and potential opportunities of each approach. |
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| Relatori: | Carlo Ricciardi |
| Anno accademico: | 2025/26 |
| Tipo di pubblicazione: | Elettronica |
| Numero di pagine: | 75 |
| Soggetti: | |
| Corso di laurea: | NON SPECIFICATO |
| Classe di laurea: | Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA |
| Ente in cotutela: | NXP Semiconductors (PAESI BASSI) |
| Aziende collaboratrici: | NXP Semiconductors |
| URI: | http://webthesis.biblio.polito.it/id/eprint/37862 |
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