Development of a UVM-Based Verification Framework for FPGA Digital Designs in Aerospace Applications

Verification has historically been a critical challenge in Application-Specific Integrated Circuit (ASIC) designs due to their fixed nature and high cost of post-silicon errors, today, the increasing complexity of Field Programmable Gate Arrays (FPGA) is driving a similar need for rigorous verification also for digital designs. As a result, traditional lab-based methodologies are proving insufficient for modern reconfigurable systems, especially in aerospace applications where they are becoming widely adopted due to their flexibility and reliability in the harsh conditions of space. This highlights the need for formal verification approaches, which can help reduce time-to-market, whereas over 60% of the design cycle is spent on verification, with nearly 40% dedicated to debugging. This thesis work presents the development of a Universal Verification Methodology (UVM)-based framework customized for functional testing of two FPGA-targeted digital designs custom developed in Argotec. The first case study focuses on verifying a custom RISC-V processor through a self-checking approach and a structured test suite, reaching 81.22% code coverage. Subsystems such as the Arithmetic Logic Unit (ALU) and external communication system were verified as standalone units, while Universal Asynchronous Receiver-Transmitter (UART)-specific verification components enabled automated interaction and diagnostics. Execution profiling and custom Python scripts supported test evaluation. The second case study targets a NAND flash memory controller featuring Advanced eXtensible Interface (AXI) and Open NAND Flash Interface (ONFI) compliant interfaces. Reusable verification components were developed for both protocols. In addition to classic operations, also key functionalities like bad block management and Error Correction Code (ECC) were tested reaching 70.7% coverage. In both cases, multiple design bugs were identified. In addition to pure Register Transfer Level (RTL) simulations, post-synthesis timing simulations were also performed, which further highlighted discrepancies compared to functional results. The modular UVM architecture enabled the creation of a reusable library of components for standard protocols such as AXI, UART, Advanced High-performance Bus (AHB) and ONFI, enhancing maintainability and scalability across the verification of different future designs. Overall, this thesis provided meaningful hybrid exposure to both functional verification and digital design. Beyond identifying issues through UVM-based testbenches, it also proposed targeted design-level solutions. This end-to-end approach enabled the consolidation of technical skills across verification, RTL analysis, and debugging, closely reflecting real-world engineering workflows.