Cross-Core Memory Validation using SBST Transparent Algorithms

This work proposes and evaluates a runtime-configurable framework for RAM testing (SRAM/DRAM) in silicon validation, with a focus on transparent March tests that preserve user data. Starting from fault models and well known March U, the algorithm is refactored into a Transparent version, based on three phases: Signature Prediction (SP), Transparent March (TS), and an Additional Transparent March (AT March), while maintaining March U coverage with overall complexity O(35n). The Transparent algorithm is based on the evaluation and comparison of different signatures, that can be computed both in HW and in SW. One of the goals of this work is to estimate the impact of the SW signature computation proposing an efficient HW implementation. The memory test environment developed supports multiple cores and bus hierarchies (e.g., ARM and RISC-V within the target SoC), enabling not only defect detection but also fault localization: by running the same test from different observation points, the method distinguishes memory-cell failures from failures along the access path. To enable reuse without recompilation, the framework relies on parametric data structures (March elements/components, patterns) and a lightweight runtime control protocol based on TLV (Type-Length-Value). A debugger is used to load onto the memory of the SoC all the configuration information needed and to trigger the test. Performance is evaluated on a 64-kB SRAM, measuring execution time on several instances of different tests (Full Transparent, Fast Transparent, SP/TS only, AT March, and non-transparent March) from different cores with a breakdown of reads/writes/signature updates. Two timing models are extracted: (i) a linear model T = α·n + C, where n is the number of operation performed and (ii) a component model T = α·n + β·Nwrite + γ·Nread + δ·Nsign + C (estimated via Non-Negative Least Squares). A look-ahead analysis with Program Counter tracing and disassembly code review on FPGA has been done, which partially confirms the results estimated with NNLS, and leads to an operational model T = (β·Nwrite + γ·Nread + δ·Nsign)·Ncells consistent with measurements. Finally, the thesis outlines a possible hardware accelerator for the signature computation of transparent March U, with preliminary analysis of speed-up and integration effort.