Development and customization of an SRAM ECC (Error-Correction-Code) intellectual property (IP).

This thesis focuses on the development of an Error Correction Code (ECC) wrapper for SRAM memories, specifically based on the SEC-DED Hamming code, to enhance reliability against soft errors. These transient faults, increasingly common due to CMOS scaling and circuit miniaturization, can lead to critical data corruption, especially in memory systems. The project began with a theoretical exploration of ECC techniques, with emphasis on the Hamming code for its balance of simplicity and effectiveness in correcting single-bit errors and detecting double-bit errors. A novel microarchitecture was proposed and implemented in SystemVerilog, following a structured digital design flow. Verification, Lint checks, and synthesis were performed to ensure correctness and evaluate the design’s impact on area, power, and speed. To support wider usability, Generator scripts were created to automatically generate wrapper instances for any data width, leading to the development of a Graphical User Interface (GUI) in Python. This tool allows users to easily customize and generate new wrapper configurations for different memory types. The project concluded with an optimization phase, refining the design for better synthesis performance and updating both the RTL and GUI accordingly. The final outcome is a fully verified, synthesized, and customizable ECC wrapper IP, equipped with a user-friendly interface.