Behavioral modelling of dinamyc virtual FIFOs

This thesis presents a behavioral model for dynamic virtual First-In-First-Out (FIFO) buffers within a descriptor-based memory system architecture, designed to support efficient context switching and preemption in high-performance hardware environments. The hardware module manages a shared pool of register buffers across multiple virtual FIFOs each representing either a cluster (processing destination) or a heap (free buffer pool) using descriptor RAM to dynamically link and organize buffer allocations. Clusters are the destinations where incoming transactions are processed. To enable efficient dispatching, the system implements a “Serial In, Parallel Out” behavior: transactions arriving from a single input are dynamically divided and routed to different clusters. The descriptor-based implementation supports dynamic FIFO sizing, allocating required memory based on traffic demand of each cluster, this reduces the overall memory requirements and chip area, with only minimal delay overhead . The behavioral model replicates the internal buffer allocation and deallocation mechanisms of the memory system, maintaining a software-level representation of the heap and cluster FIFOs. It is designed to ease debugging by improving traceability of transactions, hiding the RTL complexity from the verification team, allowing developers to monitor buffer activity and identify mismatches or protocol violations more effectively. The model is integrated into a standalone testbench environment that autonomously performs save/restore checks based solely on peripheral and debug signal sequences, without relying on external triggers. This facilitates the detection of context mismatches and protocol errors during preemption scenarios. The testing framework includes randomized and corner-case scenarios such as ping-pong context switching and back-pressure preemption, ensuring robust validation. By abstracting memory system behavior in a cycle-approximate manner, the model enables faster simulation and easier traceability of buffer transactions, ultimately aiding in the verification and debugging of complex FIFO-based designs. The final behavioral model is validated against a suite of standalone tests and is intended for use in regression environments for broader system-level verification.